1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to the circuit structure of a column decoder.
2. Description of the Background Art
Recent mainstream of memory devices is a flash memory (batch-erasable, electrically-rewritable read only memory) which is capable of storing data in a non-volatile manner. Especially, a MONOS (metal oxide nitride oxide silicon)-type memory cell has attracted attention in the field of the flash memory because of reduced costs and smaller area.
The MONOS-type memory cell is different from a floating-gate-type flash memory in that a floating gate formed from polysilicon is replaced with a gate formed from a nitride film capable of trapping charges.
FIG. 19 is a cross-sectional view of the MONOS-type memory cell MC.
Referring to FIG. 19, an oxide film 4, a nitride film 5, an oxide film 6, and a control gate 7 are stacked on a P-type semiconductor substrate 1. Oxide film 4, nitride film 5 and oxide film 6 are insulating films, and control gate 7 is formed from polysilicon. In P-type semiconductor substrate 1, N-channel diffusion regions 2, 3 are formed near the stacked portion in a self-aligned manner.
Bit lines 9 are formed in a layer located above control gate 7 via contact holes 8 electrically coupled to diffusion regions 2, 3. Bit lines 9 are formed from a metal layer. Note that this control gate functions as a word line. In order to reduce the electric resistance value of control gate 7 formed from polysilicon, it is also possible to form a metal layer having a low electric resistance value above control gate 7 so as to electrically couple the metal layer to control gate 7. However, the word line as used in the specification refers to a region of control gate 7 that does not include such a metal layer portion formed above control gate 7.
Memory cell MC thus corresponds to an N-channel field effect transistor formed on P-type semiconductor substrate 1. Such a memory cell MC is also referred to as a transistor cell.
In the structure of FIG. 19, bit lines 9 are formed in a layer located above control gate 7 via contact holes 8. However, diffusion regions 2, 3 may be replaced with bit lines formed from a diffusion layer without using contact holes 8.
FIG. 20 is a cross-sectional view of a memory cell MC# which is different from MONOS-type memory cell MC in FIG. 19.
Memory cell MC# is different from memory cell MC in that nitride film 5 serving as a charge storage layer is replaced with a granular-silicon-embedded oxide film 5# as shown in FIG. 20. Granular-silicon-embedded oxide film 5# contains a plurality of granular silicons. This memory cell MC# enables improvement in data holding characteristics and reduction in variation of threshold value in write operation as compared to memory cell MC in FIG. 19.
FIG. 21 shows a series of relations of applied voltages in write operation, read operation and erase operation of MONOS-type memory cell MC.
FIG. 21 also shows the relation between a bit to be read and a threshold voltage (Vth) of memory cell MC in read operation.
FIG. 22 illustrates write operation of MONOS-type memory cell MC.
Write operation of bit 1 will now be described with reference to FIGS. 21, 22. 0 V is applied to P-type semiconductor substrate 1, 10 V is applied to control gate 7, 5 V is applied to diffusion region 2, and 0 V is applied to diffusion region 3. Of channel electrons accelerated by a steep electric field in diffusion region 2 of the memory cell, high-energy electrons accelerated to a level equal to or higher than the barrier height of the oxide film are trapped in a region of nitride film 5 located on the side of diffusion region 2 (bit 1). Such trapping of the electrons raises the threshold voltage of memory cell MC, whereby this region of nitride film 5 is rendered in a write state for storing data xe2x80x9c0xe2x80x9d. It is herein assumed that bit 1 is xe2x80x9c0xe2x80x9d when this region of nitride film 5 is in a write state, that is, when electrons are trapped in this region of nitride film 5, and bit 1 is xe2x80x9c1xe2x80x9d when this region of nitride film 5 is in an erased state, that is, when no data is stored in this region. The following description will be given on the assumption that data in the write state is xe2x80x9c0xe2x80x9d and data in the erased state is xe2x80x9c1xe2x80x9d.
Hereinafter, write operation of bit 2 will be described.
In this case, the voltages applied to diffusion regions 2, 3 are switched. More specifically, 0 V is applied to diffusion region 2, and 5 V is applied to diffusion region 3, as shown in parenthesis in FIG. 22. In this case, electrons are trapped in a region of nitride film 5 located on the side of diffusion region 3 (bit 2). Such trapping of electrons raises the threshold voltage of memory cell MC, whereby this region of nitride film 5 is rendered in a write state for storing data xe2x80x9c0xe2x80x9d. Accordingly, bit 2 is xe2x80x9c0xe2x80x9d when this region of nitride film 5 is in the write state, that is, when electrons are trapped in this region, and bit 2 is xe2x80x9c1xe2x80x9d when this region of nitride film 5 is in the erased state.
This MONOS structure traps electrons in non-covalent bonds (dangling bonds) which are distributed in a dispersive manner within nitride film 5. Using different locations of nitride film 5 (i.e., the regions of nitride film 5 located on the side of diffusion regions 2, 3) as electron trapping regions enables implementation of data storage of 2 bits/cell.
FIG. 23 illustrates read operation of MONOS-type memory cell MC.
First, read operation of bit 1 (the region of nitride film 5 located on the side of diffusion region 2) will be described with reference to FIGS. 21, 23.
0 V is applied to P-type semiconductor substrate 1, 3 V is applied to control gate 7, 0 V is applied to diffusion region 2, and 2 V is applied to diffusion region 3. For example, when the region of nitride film 5 located on the side of diffusion region 2 is in the write state, that is, when electrons are trapped in this region of nitride film 5, memory cell MC is not turned ON due to a high threshold voltage (4 V or 4.2 V). Therefore, no current path is formed from diffusion region 3 to diffusion region 2. As a result, xe2x80x9c0xe2x80x9d can be read as bit 1. On the other hand, when the region of nitride film 5 located on the side of diffusion region 2 is in the erased state, memory cell MC is turned ON due to a low threshold voltage (1 V or 1.1 V). Therefore, a current path is formed from diffusion region 3 to diffusion region 2. As a result, xe2x80x9c1xe2x80x9d can be read as bit 1.
Read operation of bit 2 (the region of nitride film 5 located on the side of diffusion region 3) will now be described.
In this case, the voltages applied to diffusion regions 2, 3 are switched. More specifically, 0 V is applied to P-type semiconductor substrate 1, and 3 V is applied to control gate 7. Moreover, as shown in parentheses in FIG. 23, 2 V is applied to diffusion region 2, and 0 V is applied to diffusion region 3. For example, when the region of nitride film 5 located on the side of diffusion region 3 is in the write state, that is, when electrons are trapped in this region of nitride film 5, memory cell MC is not turned ON due to a high threshold voltage (4 V or 4.2 V). Therefore, no current path is formed from diffusion region 2 to diffusion region 3. As a result, xe2x80x9c0xe2x80x9d can be read as bit 2. On the other hand, when the region of nitride film 5 located on the side of diffusion region 2 is in the erased state, memory cell MC is turned ON due to a low threshold voltage (1 V or 1.1 V). Therefore, a current path is formed from diffusion region 2 to diffusion region 3. As a result, xe2x80x9c1xe2x80x9d can be read as bit 2.
Accordingly, bits 1, 2 can be read by adjusting the voltages to be applied to diffusion regions 2, 3. In other words, bits 1, 2 can be read according to whether or not a current path is formed between diffusion regions 2, 3. This enables read operation of 2 bits/cell.
FIG. 24 illustrates erase operation of MONOS-type memory cell MC.
First, erase operation of bit 1 (the region of nitride film 5 located on the side of diffusion region 2) will be described.
As shown in FIGS. 21, 24, it is herein assumed that 0 V is applied to P-type semiconductor substrate 1, 0 V is applied to control gate 7, 10 V is applied to diffusion region 2, and diffusion region 3 is rendered in an open state.
In this case, a Fowler-Nordheim current causes electrons trapped in bit 1 (i.e., the region of nitride film 5 located on the side of diffusion region 2) to move into substrate region 1 or diffusion region 2. Electrons are thus removed from the region of nitride film 5 located on the side of diffusion region 2. In this state, memory cell MC has a reduced threshold voltage.
Erase operation of bit 2 (the region of nitride film 5 located on the side of diffusion region 3) will now be described.
b V is applied to P-type semiconductor substrate 1, and 0 V is applied to control gate 7. Moreover, as shown in parenthesis in FIG. 24, diffusion region 2 is rendered in an open state, and 10 V is applied to diffusion region 3.
In this case, a Fowler-Nordheim current causes electrons trapped in bit 1 (i.e., the region of nitride film 5 located on the side of diffusion region 3) to move into substrate region 1 or diffusion region 3. Electrons are thus removed from the region of nitride film 5 located on the side of diffusion region 3. In this state, memory cell MC has a reduced threshold voltage.
Note that applying 10 V to both diffusion regions 2, 3 enables electrons to be removed from both bits 1, 2. Such erase operation is also possible.
FIG. 25 shows an example of a memory array having the above MONOS-type memory cells MC arranged in rows and columns.
As shown in FIG. 25, two bit lines are provided on both sides of each memory cell column. This structure increases the pitch of memory cell columns, causing increase in area of the memory array.
FIG. 26 is an improved example of the memory array of FIG. 25.
Referring to FIG. 26, two bit lines are provided on both sides of each memory cell column, and each bit line is shared by adjacent two memory cell columns (hereinafter, this structure is sometimes referred to as shared bit-line structure). This structure reduces the pitch of memory cell columns, enabling reduction in area of the memory array.
However, such a shared bit-line structure may cause erroneous writing to non-selected memory cells in write operation.
FIG. 27 is a conceptual diagram illustrating erroneous writing in write operation.
It is now assumed that data is to be written to a selected memory cell located between bit lines S0, S#.
As shown in FIG. 27, bit lines S0, A0 to E0, S#, A# to E# are provided corresponding to memory cell columns. More specifically, bit lines A0 to E0 are provided on the right of bit line S0, and bit lines A# to E# are provided on the left of bit line S#. Word lines WL are provided corresponding to memory cell rows.
In the illustrated example, bit line S0 is electrically coupled to power supply voltage VCC and bit line S# is electrically coupled to ground voltage GND in write operation.
In this case, a write current flows through the selected memory cell through bit lines S0, S#, whereby data is written thereto. However, since the bit lines are electrically coupled to each other through the memory cells of the selected memory cell row, a through current may flow through the non-selected memory cells via the selected memory cell in response to activation of word line WL.
FIG. 28 shows the potential levels of bit lines A0 to E0 in the case where bit line S0 is connected to power supply voltage VCC in write operation.
As shown in FIG. 28, when bit lines A0 to E0 are 0 V, these bit lines A0 to E0 are charged to power supply voltage (5 V) in response to activation of word line WL. In other words, a transient charging current, that is, a through current, flows through the non-selected memory cells of the selected memory cell row. Such a through current may cause erroneous writing to the non-selected memory cells of the selected memory cell row, that is, the memory cells other than the selected memory cell. Hereinafter, such erroneous writing to the non-selected memory cells is sometimes referred to as xe2x80x9cwrite disturbxe2x80x9d.
The above through current may flow through bit lines A# to E# located on the other side.
FIG. 29 shows the potential levels of bit lines A# to E# in the case where bit line S# is connected to ground voltage GND in write operation.
As shown in FIG. 29, when bit lines A# to E# are 5 V, these bit lines A# to E# are discharged to ground voltage (0 V) in response to activation of word line WL. In other words, a transient discharging current, that is, a through current, flows through the non-selected memory cells of the selected memory cell row. Such a through current may cause xe2x80x9cwrite disturbxe2x80x9d in the non-selected memory cells.
As in the write operation, a through current, that is, a transient charging/discharging current, flows in read operation.
FIG. 30 is a conceptual diagram illustrating a through current that flows through non-selected memory cells in read operation.
It is herein assumed that data is to be read from a selected memory cell located between bit lines S0, S#.
In the illustrated example, bit line S0 is connected to a sense amplifier and bit line S# is connected to ground voltage GND. For example, the sense amplifier supplies a voltage of 2 V, and senses data based on the amount of passing current flowing through the bit lines.
FIG. 31 shows the potential levels of bit lines A0 to E0 in the case where bit line S0 is connected to the sense amplifier (2 V) in read operation.
In the example of FIG. 31, bit lines A0 to E0 are 0 V in read operation. Since each bit line is shared by adjacent two memory cell columns, bit lines A0 to E0 are charged from 0 V to 2 V in response to activation of word line WL.
FIG. 32 shows the potential levels of bit lines A# to E# in the case where bit line S# is connected to ground voltage GND in read operation.
In the example of FIG. 32, bit lines A# to E# are 2 V in read operation. Since each bit line is shared by adjacent two memory cell columns, bit lines A# to E# are discharged from 2 V to 0 V in response to activation of word line WL.
FIG. 33 is a timing chart of a through current that flows through the sense amplifier right after read operation is started.
As shown in FIG. 33, accurate read operation cannot be assured during a period from the start of read operation to time t0, that is, a period required for a transient charging/discharging current corresponding to the above through current to disappear. This period (the period required to complete charging/discharging) results in delay in read operation.
It is an object of the present invention to provide a semiconductor memory device which prevents erroneous writing in write operation and delay in read operation in the case where the structure in which each bit line is shared by adjacent two memory cell columns is employed in order to implement a memory array having a reduced area.
According to one aspect of the present invention, a semiconductor memory device includes a memory array, a plurality of word lines, a plurality of bit lines, and a bit-line control section. The memory array has a plurality of memory cells arranged in rows and columns. The plurality of word lines are provided corresponding to memory cell rows and selectively activated. The plurality of bit lines are provided on both sides of each memory cell column so as to extend in a column direction. Each bit line is shared by adjacent two memory cell columns. Each memory cell of each memory cell row is electrically coupled between adjacent two bit lines. The bit-line control section controls setting of a voltage of the plurality of bit lines in write operation and read operation. The bit-line control section divides the plurality of bit lines into first and second groups based on a selected memory cell column including a selected memory cell. The bit-line control section sets the bit lines of the first group to one of first and second voltages and sets the bit lines of the second group to the other voltage.
In write operation and read operation, the semiconductor memory device of the present invention thus divides the plurality of bit lines into first and second bit line groups based on the selected memory cell column. The semiconductor memory device electrically couples the first bit line group to one of the first and second voltages and electrically couples the second bit line group to the other voltage.
Accordingly, a main advantage of the semiconductor memory device of the present invention is as follows: when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated. This prevents erroneous writing to the non-selected memory cells in write operation. Moreover, the above structure eliminates the need to delay the time to start sensing operation of a sense amplifier in read operation by a prescribed period in view of a charging/discharging current. This enables improvement in read operation speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.